The energy consumption of DRAM is a critical concern in modern computingsystems. Improvements in manufacturing process technology have allowed DRAMvendors to lower the DRAM supply voltage conservatively, which reduces some ofthe DRAM energy consumption. We would like to reduce the DRAM supply voltagemore aggressively, to further reduce energy. Aggressive supply voltagereduction requires a thorough understanding of the effect voltage scaling hason DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding andexploiting the latency and reliability characteristics of modern DRAM when thesupply voltage is lowered below the nominal voltage level specified by DRAMstandards. Using an FPGA-based testing platform, we perform an experimentalstudy of 124 real DDR3L (low-voltage) DRAM chips manufactured recently by threemajor DRAM vendors. We find that reducing the supply voltage below a certainpoint introduces bit errors in the data, and we comprehensively characterizethe behavior of these errors. We discover that these errors can be avoided byincreasing the latency of three major DRAM operations (activation, restoration,and precharge). We perform detailed DRAM circuit simulations to validate andexplain our experimental findings. We also characterize the variousrelationships between reduced supply voltage and error locations, stored datapatterns, DRAM temperature, and data retention. Based on our observations, we propose a new DRAM energy reduction mechanism,called Voltron. The key idea of Voltron is to use a performance model todetermine by how much we can reduce the supply voltage without introducingerrors and without exceeding a user-specified threshold for performance loss.Voltron reduces the average system energy by 7.3% while limiting the averagesystem performance loss to only 1.8%, for a variety of workloads.
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